
interface Axi4LiteIf #( parameter AW = 32)(
    input wire clk
);
    logic rst_n;
    logic [AW-1:0] awaddr;
    logic [2:0] awprot;
    logic awvalid , awready;
    logic [31:0] wdata;
    logic [3:0] wstrb;
    logic wvalid , wready;
    logic [1:0] bresp;
    logic bvalid , bready;
    logic [AW-1:0] araddr;
    logic [2:0] arprot;
    logic arvalid , arready;
    logic [31:0] rdata;
    logic [1:0] rresp;
    logic rvalid , rready;

    modport master(
        input clk, rst_n,
        output awaddr, awprot, awvalid, input awready,
        output wdata, wstrb, wvalid, input wready,
        input bresp, bvalid, output bready,
        output araddr, arprot, arvalid, input arready,
        input rdata, rresp, rvalid, output rready
    );
    modport slave(
        input clk, rst_n,
        input awaddr, awprot, awvalid, output awready,
        input wdata, wstrb, wvalid, output wready,
        output bresp, bvalid, input bready,
        input araddr, arprot, arvalid, output arready,
        output rdata, rresp, rvalid, input rready
    );

endinterface

